1. Field of the Invention
The present invention relates to a level shifter, and more particularly, to a CMOS level shifter without DC current flow.
2. Description of the Prior Art
With advanced complementary metal oxide semiconductor (CMOS) technology, more and more circuits are integrated into a single chip. Therefore, the issue for heat dissipation of the chips is important. A simple way to reduce the heat is to decrease the working voltage of the chips. However, to increase the noise margin and avoid the noises from the external environment, the I/O circuits of the chips are usually applied higher voltage than the kernel circuits. Therefore, most of the chips are applied two working voltages. Level shifters, hence, are necessary to translate signals between two voltage supply domains.
Please refer to FIG. 1, which is a circuit diagram of a level shifter 70 according to the prior art. The level shifter 70 is used to translate signals between two voltage supply domains and has a current mirror structure. The level shifter 70 has an inverter 2, a current mirror 10, and a switch module 20. The inverter 2 outputs an inverted signal by inverting an input signal from an input node 1. The operation of the switch module 20 is controlled by the input signal from the input node 1 and the inverted signal from the output of the inverter 2. The current mirror 10 is composed of two gate-coupled PMOS transistors 111 and 12. The gate of the PMOS transistor 11 is further coupled to the drain of the PMOS transistor 11. The current mirror 10 is controlled by the two nodes 3 and 4. The switch module 20 comprises two NMOS transistors 21 and 22. The drains of the two NMOS transistors are respectively coupled to the node 3 and the node 4, and the gates of the two NMOS transistors are respectively biased by the input signal from the node 1 and the inverted signal from the output of the inverter 2. When the voltage level of the input signal from the node 1 is pulled up from the grounded level to VDDAL, the NMOS transistor 21 is turned on and the NMOS transistor 22 is turned off. In such case, the NMOS transistor 21 can be taken as a small resistor. According to Ohm's law, the current flows through the NMOS transistor 21 is equal to (VDDAH−|VGS|)/R, where VGS is the voltage difference between the gate and the source of the PMOS transistor 11, and R is the equivalent turn-on resistance of the NMOS transistor 21. The current flowing through the NMOS transistor 21 is mirrored to the PMOS transistor 12 of the current mirror 10 so that the voltage levels of the node 4 and an output terminal 9 are pulled up to VDDAH. If the voltage level of the node 1 keeps at VDDAL, the level shifter 70 generates a DC current which flows from the power terminal VDDAH through PMOS transistor 11 and the NMOS transistor 21 to a grounding terminal GND. In addition, when the voltage level of the node is pulled down from VDDAL to the grounded level, the NMOS transistor 21 is turned off and the NMOS transistor 22 is turned on. Meanwhile, because the NMOS transistor 21 is turned off, no current flows through the PMOS transistor 11. Therefore, the current mirror 10 and the PMOS transistor 12 are turned off. The voltage level of the output terminal, hence, is pulled down to grounded level via the turned on NMOS transistor 22.
Please refer to FIG. 2, which is a circuit diagram of another level shifter 80 according to the prior art. The level shifter 80 is disclosed in U.S. Pat. No. 5,469,080 “LOW-POWER, LOGIC SIGNAL LEVEL CONVERTER”. The level shifter 80 uses a PMOS transistor 6 to control the electrical connection between the two nodes 3 and 5. The gate of the PMOS transistor 6 is feedback controlled by the node 4 so that the DC current flow is eliminated in a specific situation. When the node 1 is low, i.e. grounding, the NMOS transistor 22 is turned on so that the voltage level of the node 4 is pulled down to the grounded level. Then, the PMOS transistor 6 is turned on. When the voltage level of the node 1 is pulled up from the grounded level to VDDAL, the NMOS transistor 21 is turned on and the NMOS transistor 22 is turned off. At the moment, because the PMOS transistor 6 is still turned on, a transient current flows from the power terminal VDDAH through the PMOS transistor 11, the PMOS transistor 6 and the NMOS transistor 21 to the grounded terminal GND. The transient current is mirrored to the PMOS transistor 12 of the current mirror 10 so that the voltage level of the node 4 is pulled up to approach to VDDAH. Without concerning about the body effect of the transistors and assume all the PMOS transistors are identical, the PMOS transistor 6 is turned off when the voltage level of the node 4 is pulled up to (VDDAH−2Vtp), where Vtp is the threshold voltage of the PMOS transistors. However, when the PMOS transistor 6 is turned off, it is impossible to keep the current mirror 10 being turned on. In the situation, the voltage level of the node 4 stays at (VDDAH−2Vtp) and cannot be further pulled up to VDDAH. Therefore, the level shifter 80 is not a full-swing level shifter, and the circuits drived by the level shifter 80 may have DC current issues. Oppositely, when the voltage level of the node 1 is pulled down from VDDAL to the grounded level, the NMOS transistor 21 is turned off and the NMOS transistor 22 is turned on. Then, the voltage level of the node 4 is pulled down to the grounded level via the NMOS transistor 22. In this situation, the PMOS transistor 6 is turned on by the node 4, so it is impossible that NMOS transistor 21 and the PMOS transistor 6 are turned on at the same time. And, there is not any DC current generated.
Please refer to FIG. 3, which is a circuit diagram of another level shifter 90 according to the prior art. The level shifter 90 is disclosed in U.S. Pat. No. 6,480,050 “LEVEL SHIFTER WITHOUT QUIESCENT DC CURRENT FLOW”. The level shifter 90 is based on the level shifter 70 shown in FIG. 1. The level shifter 90 has all the elements of the level shifter 70, moreover, a PMOS transistor 34, two inverters 31, 32, and a PMOS transistor 14. When the voltage level of the input node 1 is equal to VDDAL, because the inverters 31 and 32 are controlled by the node 4, the PMOS transistor 14 is turned off to avoid DC current. Meanwhile, the PMOS transistor 34 is turned on, another DC current path is occurred, i.e. the dotted line in FIG. 3. A DC current I flows from the power terminal VDDAH through the PMOS transistor 34, the PMOS transistor 12, the PMOS transistor 11, and the NMOS transistor 21 to the grounded terminal GND.